`timescale 1ns / 1ns

module fc2_fc3_bridge(
    input wire clk,
    input wire reset,
    input wire [47:0] in_data,
    input wire [4:0] in_addr,
    input wire in_wren,
    output reg [1535:0] out_data
    );

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            out_data <= 1536'b0;
        end else if (in_wren) begin
            // 地址0放在最高位，因为权重是从左往右读出来的
            out_data[1535 - 48 * in_addr -: 48] <= in_data;
        end
    end

endmodule
